features: applic ations: FTP10N40 n-c hannel m o sf et ft p10n 40 rev. b oct. 20 06 ? 200 6 in power semicon ductor co., l t d . ? balla st an d ligh ting ? dc-ac inverter ? ro hs c o mp l i a n t ? low on re sistan ce ? low ga te cha r g e ? pe ak cu rr en t vs pulse width cur v e ? in ductive switching cu rves lead free package and finish v dss r ds( o n) (m a x . ) i d 40 0v 0 . 55 ? 10a orderin g info rmati o n part number package b rand FTP10N40 to-220 FTP10N40 absolute m a ximum r a tings t c = 25 o c unle ss otherwise specified symbo l para mete r m aximum units v ds s d r a i n - t o - s o u r c e v o l t a g e ( n o t e * 1 ) 4 0 0 v i d continu ous drai n current 10 a i d @ 10 0 o c c ontinu ous drai n current fig u re 3 i dm pulsed d r a i n cu rre n t, v gs @ 1 0 v ( n o t e * 2 ) f i g u r e 6 p d power dissip a ti on 13 9 w derating f a ctor abo ve 25 o c1 . 1 1 w / o c v gs g a te -to - so ur ce vol t ag e 30 v e as single pu lse avalan che eng e rgy l=5 00 h , i d = 28.3 amps 20 0 m j i as pulsed aval anche r a ting figu re 8 d v/ d t p e a k d i o d e r e co v e r y d v/ d t ( n o t e * 3 ) 3 . 0 v / n s t l t pkg m a ximum temper ature for soldering le ads at 0.063i n (1.6mm) from case for 10 secon d s package body for 10 seconds 30 0 26 0 o c t j a nd t st g ope r ating jun c tio n and storag e temp erature ran g e -5 5 to 150 thermal resist ance symbol par a meter m in. t yp. m ax. u nits test con d ition s r jc ju nct i on-to-case -- -- 0.9 o c /w water cooled heatsink, p d adjusted for a peak ju ncti on tempera t ure o f + 150 o c . r ja jun ctio n -to-amb i ent -- -- 6 2 1 cubic foot chambe r, free air. caution: stresses greater than thos e listed in the ? a bso l ute maxi mum ra tings? table may cause p e rmanent damage to th e device. d g s to -2 20 no t to scale d g s pb http://
ft p10n 40 rev. b oct. 2 006 page 2 of 9 ? 20 06 inpowe r semico nductor co., ltd . on characteristics t j =25 o c u n less o t herwise sp ecif ied symb ol pa rameter m in. t yp. m ax. u nits test con d itions r ds ( o n ) sta t ic dra i n-to-source on-resistance fi gure 9 a nd 10 . -- 0. 4 5 0. 5 5 ? v gs =10 v , i d =6a (note *4) v gs ( t h ) ga te t h resh old vol t ag e, figu re 12. 2.0 - - 4 .0 v v ds = v gs , i d = 250 a g f s f o r ward t r a n scond ucta nce -- 9.3 -- s v ds =15 v , i d = 10a (note *4) off characterist i c s t j =25 o c un less ot herwise sp ecifi ed symbol pa rameter m in. t yp. m ax. u nits test con d itions bv dss drain - to-sou rce bre a kdo w n voltage 40 0 - - - - v v gs =0 v, i d = 250 a ? bv ds s / ? t j breakdo wnvoltag e te mp erature c o ef fi ci e n t , f i gu re 1 1 . -- 0.5 - - v/ o c reference to 25 o c, i d = 2 50 a i dss drain - to-sou rce lea ka ge cu rre n t -- -- 25 a v ds =40 0 v, v gs =0v -- -- 25 0 v ds = 320 v, v gs =0 v t j =12 5 o c i gss ga te -to-sou r ce forw ard lea kage -- -- 10 0 na v gs =+ 30 v ga te -to-sou r ce reverse l eakag e - - - - - 10 0 v gs = -30 v resistive switching characteri stics esse ntial l y indep enden t of operati ng te mper ature symb ol pa rameter m in. t yp. m ax. u nits test con d itions t d( on ) turn-on delay time -- 22 -- ns v dd =2 00 v t rise rise time -- 45 -- i d = 10a t d( o ff) turn-off delay tim e -- 84 -- v gs =10 v t fall fall time -- 38 -- r g =1 2 ? dynamic characteristics essentially ind epend ent o f opera t ing temp erature symb ol pa rameter m in. t yp. m ax. u nits test con d itions c is s in put cap a citance - - 1 090 -- pf v gs =0 v c oss ou tp ut c apacitan ce -- 18 0 - - v ds =25 v c rss reverse t r ansfer cap a citance - - 1 1 0 -- f= 1 . 0 m h z f i gure 1 4 q g to ta l gat e ch arge -- 4 6 .7 -- nc v dd =20 0 v q gs ga te -to-sou r ce charg e -- 7.4 - - i d=1 0 a v gs =10 v q gd ga te -to-dra i n ( ?mille r? ) charge -- 2 3 .4 -- f i gure 1 5
ft p10n 40 rev. b oct. 2 006 page 3 of 9 ? 20 06 inpowe r semico nductor co., ltd . source-drai n diode characteristics t c =25 o c unl ess othe rwi s e specifie d symbol pa rameter m in. t yp. m ax. u nits test con d itions i s con t in uous sou r ce current (body dio de) -- -- 10 a i ntegral p n -dio de i sm maximum pulsed cu rrent (bo d y diod e) -- -- 40 a i n m o sfet v sd diod e fo rward voltag e -- -- 1.5 v i s = 10a, v gs =0 v t rr reverse recovery time -- 330 4 95 ns v gs =0 v q rr r e ve rse re co ve ry c h ar ge -- 6 6 0 9 90 nc i f =1 0a, d i /d t= 100 a/s notes: *1 . t j = +25 o c t o +1 50 o c. *2. repetitiv e rating; pulse w i dth lim ited by maximu m junction tem per atur e. *3 . i sd = 10a di/dt < 100 a/s, v dd < bv dss , t j =+150 o c. *4. pulse width < 380s; duty cycle < 2%.
ft p10n 40 rev. b oct. 2 006 page 4 of 9 ? 20 06 inpowe r semico nductor co., ltd . t p , r e cta ngular pulse dura tion (s) t c , case temperature ( o c ) maximum continuous drain current vs case temperature p d , powe r d i ssipation ( w ) t c , c ase tempe r atur e ( o c ) v ds , d r ain- to-sour ce volta ge ( v ) 0 i d , drai n cu rren t (a) i d , d r ain cur r ent (a) rd s ( on), drain-to- s ource on resistance ( ?) v gs , gate -to-sour ce volta ge ( v ) f i gu re 4 . t yp i cal ou tput c hara cteri sti cs typ i ca l dra i n-to -sou rce on re sistan ce vs gate voltag e an d d r ain cu rrent 7 2 0 75 1. 000 0. 100 0. 010 0 maximum power dis sipation vs case temperature 68 1 6 25 50 75 100 12 5 150 25 50 75 100 125 15 0 1e-0 5 1 e-04 1e -03 1 e-02 1e -01 1e + 00 1e+01 5 notes : duty f a ctor: d = t1 / t 2 p eak t j =p dm x z jc x r jc +t c 20 % 10% 5 % 2% single pulse 1% p dm t 1 t 2 pulse dura t i on = 2 50 s d u t y fa cto r = 0. 5% ma x t c = 25 o c fi gu re 1 . ma ximum effecti v e t h e rmal impe da nce , j uncti on-to -case v gs = 5.5v v gs = 6. 5 v v gs = 6. 0v 2. 3 0. 8 4 i d = 2 0 a i d = 1 0 a i d = 5 a z jc , th ermal impedan ce ( n ormalized) pulse dura tion = 2 5 0 s duty fact o r = 0 . 5 % m a x t c = 25 o c 50% 0. 001 0. 3 8 25 50 25 5 9 fi gu re 2. f i g u r e 3 . f i g u r e 5 . duty factor 05 10 15 20 15 10 12 14 18 2 0 3 v gs = 5. 0 v 1. 3 150 10 0 12 5 10 6 4 1 v gs = 7.0v v gs = 15 v v gs = 10 v v g s = 7 . 5 v 10 20 1.8
ft p10n 40 rev. b oct. 2 006 page 5 of 9 ? 20 06 inpowe r semico nductor co., ltd . t p , pulse width (s) i dm , peak current (a) 100 0 1 v gs , gate- to-sour ce voltage ( v ) i d , drain-to- s ource c u rre nt ( a ) t av , time in avalanche (s) i as , avala n che cur r ent (a) 10 1 i d , dr ain curr ent ( a ) t j , ju nction t e mpera t ure ( o c ) r ds(on) , dr ain- to-source resistance (n ormalized) 1. 4 0. 8 0.4 0. 6 r ds(on) , drain-to- s o urce on resistance ( ? ) 14 2 0 fi gu re 7 . t ypi cal tra n sfer c h a r acteri stics 1e- 6 10 e - 3 10e -6 100e -6 - 7 5 - 50 -2 5 0 25 5 0 75 100 1 2 5 1 50 05 1 5 34 6 7 1 0 e-6 1 00e- 6 1 e -3 1 0 e-3 100e -3 1 e +0 10e+0 30 p u l s e dura tio n = 2 5 0 s du ty cy cl e = 0.5 % m a x v ds = 10 v sta r ting t j = 25 o c st a r ti ng t j = 1 5 0 o c pul s e duration = 250 s duty cycle = 0.5% max v gs = 10v, i d = 10a 8 v gs = 10 v 2. 2 1. 8 1. 6 pul s e dura tio n = 2 s du ty cy cle = 0.5 % m a x t c =2 5 c if r= 0: t av = (l i as )/ ( 1 . 3 bv dss -v dd ) if r 0: t av = (l/r) ln[i as r)/(1.3bv dss -v dd )+1 ] r equals total series resistance of drain circuit 10 2. 6 2. 4 1. 2 10 0 0. 2 5 tr ans c onduc tan c e m a y l i mit curre nt in th i s re gion for tem p e r a t ure s ab o v e 25 o c de rat e pe a k curre nt a s foll ows : ii 25 15 0 t c ? 12 5 - --- --- -- --- -- --- -- -- - = fi gure 6. maxi mum pe ak cu rren t cap a b ility 20 18 16 1. 2 5 1. 0 0 -5 5 o c +25 o c +150 o c v gs = 1 0 v 0. 50 unclamped inductive sw itchin g c a p abi lity f i g u r e 8 . t ypi cal drai n-to-so u rce on resistanc e vs jun cti on te mpe r at ure t ypi cal drai n-to-so u rce on resistance vs drai n current figu re 9 . figu re 1 0 . 12 1e-3 25 1. 0 5 10 8 6 4 0. 75 2. 0 10 0 10 20
ft p10n 40 rev. b oct. 2 006 page 6 of 9 ? 20 06 inpowe r semico nductor co., ltd . i sd , reverse drain current (a) c, capacitance (pf) i d , drain current (a) v gs(th) , threshold voltage (normalized) t j , junction te mperatur e ( o c) v ds , dr ain- to-sour ce voltag e ( v ) v sd , sour ce- t o-d r ain voltag e ( v ) q g , total gate c harge (nc ) t j , junction t e mperatur e ( o c) 1. 1 1.2 1. 0 0.8 30 10 .0 1. 0 0. 1 12 8 2 0 1. 1 0 1. 0 5 1. 00 0. 95 0. 90 0. 9 0. 6 10 -75 - 50 -25 0. 0 25 50 75 100 125 15 0 -7 5 - 5 0 -2 5 5 0 1 00 75 125 15 0 25 0. 0 1 10 10 0 0. 01 1 10 1 0 0 0 0 . 2 0 . 4 0. 6 0 .8 1. 0 1 . 2 20 10 4 6 10 v gs = 0 v i d = 250 a v g s = v d s i d = 2 5 0 a t j = max rated, t c = 25 o c op eratio n in this are a m a y be li mited by r ds(on) 1 0 s 1 0 0 s 1 . 0 m s d c c oss c rs s c iss v gs = 0 v , f = 1 m h z c iss = c gs + c gd c oss ? c ds + c gd c rs s = c gd i d = 10 a +150 o c + 2 5 o c 0 1. 15 1 0 m s 1 000 10 00 100 1 000 10 000 10 100 .0 v ds , drain voltage (v) 0. 7 40 30 v gs = 0 v 1. 6 60 40 v ds = 10 0v v ds = 20 0v v ds = 30 0v - 5 5 o c bv dss , drain-to-source breakdown voltage (normalized) v gs , gate-to-source voltage (v) t y p ical brea kdow n vo ltag e vs jun c ti on te mpe r at ure typi cal threshold vol t age vs jun cti on te mpe r at ure fi gu re 11 . fi gu re 12 . 50 typical capaci tance vs dra i n-to -sou rce vo l t a g e maximum forward bias safe o p e r at in g are a figu re 1 3 . fi gu re 1 4. typi ca l g a te c h a r ge v s ga te-to-so urce volta g e typ i ca l bo dy di ode t r ans fe r characteristics fi gure 15 . figu re 1 6 . 0. 1 1. 4 20 50
ft p10n 40 rev. b oct. 2 006 page 7 of 9 ? 20 06 inpowe r semico nductor co., ltd . f i gu re 17. ga te c harge t e st circuit f ig ure 18 . gate charg e wave fo rm figure 19. resistive switching test circuit figure 20. resistive switching waveforms test circuits and waveforms v ds v gs t d( on ) t d(off ) t ri se t fall 90 % 10 % v gs( t h) q gs q gd v gs v ds i d q g miller region v dd v ds i d v gs 1 ma d.u.t. v dd v ds r l v gs d.u.t. r g
ft p10n 40 rev. b oct. 2 006 page 8 of 9 ? 20 06 inpowe r semico nductor co., ltd . figure 21. diode reverse recovery test circuit fi gure 2 2 . di ode re verse recove ry w a veform fi gure 23 . un clamped ind u cti v e switch ing t e st c i rcui t f ig ure 24 . un cl amped ind u cti v e switch ing w a veforms te st circuits an d waveforms i d q rr t rr bv dss v gs i as v dd t p t av 2 2 l i e as as = 0 v dd d o uble pulse i d l di/dt adj. d. u . t. current pump v dd d.u.t. bv dss i as v gs l 50 ? series switch (m o s f e t) co mmu ta tin g di o d e di/dt = 100a/a
ft p10n 40 rev. b oct. 2 006 page 9 of 9 ? 20 06 inpowe r semico nductor co., ltd . disclaimers: inpow e r s e miconductor co. , l t d ( i p s ) reser v es the right to make chang e s w itho u t no tice in ord e r to i m p r ov e reliab ili ty , fun c ti on o r d e sig n an d t o di scon ti nu e any pr od uct or serv ice w i t h o u t n o ti ce. cust omer s sho u l d ob tai n t h e latest rel e v a nt i n fo rmatio n before orders and shou ld v e rify t h at such inform ation is current and c o mplete. all products are sold subject to ips? s terms and cond iti ons su ppl ied at the ti me of o r der ack nowl e dgement. inpower semi co ndu ctor co., ltd w a rrants p e rfo r mance of i t s ha rdware product s to the speci ficat ion s at th e ti me o f sale, t e st ing , rel i abil ity and q u ali t y control are us ed to the extent ips deems necessary to suppor t this warrantee. except where agreed upon by contractual agree m ent, testing of all parameters of each product is no t necessarily performed. inpower semi cond uctor c o ., lt d d o es n o t assu me any liab ilit y aris in g fro m the use o f any pro duct or ci rcui t d e si gns describ e d herein. customers are respons i ble for thei r produ cts and app licati ons u s ing ips? s compon ents. t o minimize risk , cu stomers must provi de adequat e d e si gn and op erati ng safegu ards. inpower semicond ucto r co., ltd does not warrant o r co nvey any l i cense ei ther exp r essed or impli e d u nder i t s p a t e nt ri ght s, n o r th e righ ts o f oth e rs. reprodu ctio n o f informat ion in ips? s data sheets o r data bo oks is p e rmissi ble onl y if repro ducti on is without modification or alteration. reproduc tion of this informat ion with any alterati on is an unfair and deceptive business practice. inpower semicondu ct o r co. , l t d i s no t r e sp on si b l e or l i a bl e f o r suc h alt e r e d do cu men t ati o n. r e sal e of ips? s pro ducts w ith statements di f f erent from or beyo nd t h e paramet e rs stated by inpower semi co ndu ctor co., lt d for t h at product o r servi ce v o ids all exp r ess o r impli e d warrantees for the asso ciated ips? s pro duct or service and i s un fair a nd decepti ve business pract ice. inpower semi conductor c o ., ltd is not responsible or li able for any such statements. life support policy: inpow e r semico nduct o r co., ltd ? s pro ducts are no t au tho r ized for use as criti cal co mp onent s i n l i fe sup port devices or systems wi thou t the expressed w r it ten appr ov al o f in po wer semico nduct o r co ., lt d. a s used her e i n : 1. life support dev i ces o r systems are dev i ces o r sy stems whi c h: a. are intended f o r s u r g ical i m p l an t in t o th e hu man bo d y , b. su pport or sus t ain life, c. whose failure to pe rform when properly used in accordance with instructions for used provided in the label i ng , can be reasonab l y expect ed to resul t in sign ifi cant injury to the user . 2. a crit ical componen t is an y comp onen t of a life sup port device or sy st em who s e failure to perform can be reason ably expected to caus e the failu re of th e l i fe supp ort d e vice or system, o r to af fect its safety or ef fectivenes s.
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